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automotive power data sheet rev. 1.2, 2014-07-03 tle42744 low dropout linear voltage regulator tle42744dv50 tle42744gv50 tle42744ev50 tle42744gv33 tle42744dv33 TLE42744GSv33
tle42744 type package marking tle42744dv50 pg-to252-3 42744v5 tle42744gv50 pg-to263-3 42744v5 tle42744ev50 pg-ssop-14 exposed pad 42744v5 tle42744dv33 pg-to252-3 42744v33 tle42744gv33 pg-to263-3 42744v33 TLE42744GSv33 pg-sot223-4 42744v33 data sheet 2 rev. 1.2, 2014-07-03 pg-to252-3 pg-to263-3 pg-ssop-14 exposed pad pg-sot223-4 low dropout linear voltage regulator 1overview features ? very low current consumption ? output voltages 5 v and 3.3 v 2% ? output current up to 400 ma ? very low dropout voltage ? output current limitation ? reverse polarity protection ? overtemperature shutdown ? wide temperature range from -40 c up to 150 c ? green product (rohs compliant) ? aec qualified description the tle42744 is a monolithic integrated low dropout voltage regulator for load currents up to 400 ma. an input voltage up to 40 v is regulated to v q,nom = 5 v / 3.3 v with a precision of 2%. t he device is designed for the harsh environment of automotive applications. therefore it is protected against ov erload, short circuit and overtemperature conditions by the implemented outpu t current limitation and the overtemperature shutdown circuit. the tle42744 can be also us ed in all other applicat ions requiring a stabilized 5 v / 3.3 v voltage. due to its very low quiescent current the tle42744 is dedicated for use in applications permanently connected to v bat .
tle42744 block diagram data sheet 3 rev. 1.2, 2014-07-03 2 block diagram figure 1 block diagram aeb01959 gnd q bandgap reference control amplifier sensor temperature buffer saturation control and protection circuit
data sheet 4 rev. 1.2, 2014-07-03 tle42744 pin configuration 3 pin configuration 3.1 pin assignment pg-to252-3, pg-to263-3 and pg-sot223-4 figure 2 pin configuration (top view) 3.2 pin definitions and functions pg-t o252-3, pg-to263-3 and pg-sot223-4 pin no. symbol function 1i input block to ground directly at the ic with a ceramic capacitor 2gnd ground internally connected to heat slug 3q output block to ground with a capacitor close to the ic terminals, respecting the values given for its capacitance and esr in ?functional range? on page 6 4 / heat slug ? heat slug internally connected to gnd; connect to gnd and heatsink area aep02561 13 q gnd gnd q aep02281 pinconfig_pg-sot223- 4.vsd 123 4 i gnd gnd q
tle42744 pin configuration data sheet 5 rev. 1.2, 2014-07-03 3.3 pin assignment pg -ssop-14 exposed pad figure 3 pin configuration (top view) 3.4 pin definitions and functi ons pg-ssop-14 exposed pad pin no. symbol function 1, 2, 3, 5, 6, 7 n.c. not connected can be open or connected to gnd 4gnd ground 8, 10, 11, 12, 14 n.c. not connected can be open or connected to gnd 9q output block to ground with a capacitor close to the ic terminals, respecting the values given for its capacitance and esr in ?functional range? on page 6 13 i input block to ground directly at the ic with a ceramic capacitor pad ? exposed pad connect to gnd and heatsink area n.c. n.c. q n.c. n.c. n.c. i n.c. n.c. n.c. n.c. gnd n.c. n.c. 1 2 3 4 5 6 7 14 9 10 11 12 13 8 tle7274-2_pinconfig_ssop- 14.svg
data sheet 6 rev. 1.2, 2014-07-03 tle42744 general product characteristics 4 general product characteristics 4.1 absolute maximum ratings notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. 4.2 functional range table 1 absolute maximum ratings 1) t j = -40 c to 150 c; all voltages with respec t to ground, (unless otherwise specified) 1) not subject to production test, specified by design parameter symbol values unit note / test condition number min. typ. max. input i voltage v i -42 ? 45 v ? p_4.1.1 output q voltage v q -1 ? 40 v ? p_4.1.2 temperature junction temperature t j -40 ? 150 c ? p_4.1.3 storage temperature t stg -50 ? 150 c ? p_4.1.4 esd susceptibility esd absorption v esd,hbm -4 ? 4 kv human body model (hbm) 2) 2) esd susceptibility human body model ?h bm? according to aec-q100-002 - jesd22-a114 p_4.1.5 esd absorption v esd,cdm -1000 ? 1000 v charge device model (cdm) 3) at all pins 3) esd susceptibility charged device model ?cdm? according to esda stm5.3.1 p_4.1.6 table 2 functional range parameter symbol values unit note / test condition number min. typ. max. input voltage v i 5.5 ? 40 v tle42744dv50, tle42744gv50, tle42744ev50 p_4.2.1 input voltage v i 4.7 ? 40 v tle42744gv33, tle42744dv33, TLE42744GSv33 p_4.2.2
tle42744 general product characteristics data sheet 7 rev. 1.2, 2014-07-03 note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . output capacitor?s requirements for stability c q 22 ? f 1) p_4.2.3 output capacitor?s requirements for stability esr(c q ) ?3 ? 2) p_4.2.4 junction temperature t j -40 150 c ? p_4.2.5 1) the minimum output capacitance requirement is appl icable for a worst case capacitance tolerance of 30% 2) relevant esr value at f =10khz table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. tle42744dv50, tle42744dv33 (pg-to252-3) junction to case 1) r thjc ? 3.6 ? k/w measured to heat slug p_4.3.1 junction to ambient 1) r thja ? 27 ? k/w fr4 2s2p board 2) p_4.3.2 junction to ambient 1) r thja ? 115 ? k/w fr4 1s0p board, footprint only 3) p_4.3.3 junction to ambient 1) r thja ? 52 ? k/w fr4 1s0p board, 300 mm2 heatsink area 3) p_4.3.4 junction to ambient 1) r thja ? 40 ? k/w fr4 1s0p board, 600 mm2 heatsink area 3) p_4.3.5 tle42744gv50, tle42744gv33 (pg-to263-3) junction to case 1) r thjc ? 3.6 ? k/w measured to heat slug p_4.3.6 junction to ambient 1) r thja ? 22 ? k/w fr4 2s2p board 2) p_4.3.7 junction to ambient 1) r thja ? 74 ? k/w fr4 1s0p board, footprint only 3) p_4.3.8 junction to ambient 1) r thja ? 42 ? k/w fr4 1s0p board, 300 mm2 heatsink area 3) p_4.3.9 junction to ambient 1) r thja ? 34 ? k/w fr4 1s0p board, 600 mm2 heatsink area 3) p_4.3.10 table 2 functional range (cont?d) parameter symbol values unit note / test condition number min. typ. max.
data sheet 8 rev. 1.2, 2014-07-03 tle42744 general product characteristics tle42744ev50 (pg-ssop-14 exposed pad) junction to case 1) r thjc ? 7 ? k/w measured to exposed pad p_4.3.11 junction to ambient 1) r thja ? 43 ? k/w fr4 2s2p board 2) p_4.3.12 junction to ambient 1) r thja ? 120 ? k/w fr4 1s0p board, footprint only 3) p_4.3.13 junction to ambient 1) r thja ? 59 ? k/w fr4 1s0p board, 300 mm2 heatsink area 3) p_4.3.14 junction to ambient 1) r thja ? 49 ? k/w fr4 1s0p board, 600 mm2 heatsink area 3) p_4.3.15 TLE42744GSv33 (pg-sot223-4) junction to case 1) r thjc ? 17 ? k/w measured to heat slug p_4.3.16 junction to ambient 1) r thja ? 54 ? k/w fr4 2s2p board 2) p_4.3.17 junction to ambient 1) r thja ? 139 ? k/w fr4 1s0p board, footprint only 3) p_4.3.18 junction to ambient 1) r thja ? 73 ? k/w fr4 1s0p board, 300 mm2 heatsink area 3) p_4.3.19 junction to ambient 1) r thja ? 64 ? k/w fr4 1s0p board, 600 mm2 heatsink area 3) p_4.3.20 1) not subject to production test, specified by design. 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 bo ard with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. 3) specified r thja value is according to jedec jesd 51-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm 3 board with 1 copper layer (1 x 70m cu). table 3 thermal resistance (cont?d) parameter symbol values unit note / test condition number min. typ. max.
tle42744 electrical characteristics data sheet 9 rev. 1.2, 2014-07-03 5 electrical characteristics 5.1 electrical character istics voltage regulator table 4 electrical characteristics v i = 13.5 v; t j = -40 c to 150 c; all voltages with respect to ground (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output q output voltage v q 4.9 5.0 5.1 v tle42744dv50, tle42744gv50, tle42744ev50 5ma< i q <400ma 6v< v i <28v p_5.1.1 output voltage v q 4.9 5.0 5.1 v tle42744dv50, tle42744gv50, tle42744ev50 5ma< i q <200 ma 6v< v i <40v p_5.1.2 output voltage v q 3.23 3.3 3.37 v tle42744gv33, tle42744dv33, TLE42744GSv33; 5ma< i q <400ma 4.7 v < v i <28v p_5.1.3 output voltage v q 3.23 3.3 3.37 v tle42744gv33, tle42744dv33, TLE42744GSv33; 5ma< i q <200 ma 4.7 v < v i <40v p_5.1.4 dropout voltage v dr ? 250 500 mv tle42744dv50, tle42744gv50, tle42744ev50 i q = 250 ma v dr = v i ? v q 1) p_5.1.5 load regulation ? v q, lo ? 20 50 mv tle42744dv50, tle42744gv50, tle42744ev50; i q = 5 ma to 400 ma v i =6v p_5.1.6 load regulation ? v q, lo ? 40 70 mv tle42744gv33, tle42744dv33, TLE42744GSv33; i q = 5 ma to 300 ma p_5.1.7 line regulation ? v q, li ? 1025mv v l = 12 v to 32 v i q =5ma p_5.1.8
data sheet 10 rev. 1.2, 2014-07-03 tle42744 electrical characteristics output current limitation i q 400 600 1100 ma 1) p_5.1.9 power supply ripple rejection 2) psrr ?60?db f r =100hz; v r = 0.5 vpp p_5.1.10 temperature output voltage drift ? 0.5 ? mv/k ? p_5.1.11 overtemperature shutdown threshold t j,sd 151? 200c t j increasing 2) p_5.1.12 overtemperature shutdown threshold hysteresis t j,sdh ?25?c t j decreasing 2) p_5.1.13 current consumption quiescent current i q = i i ? i q i q ?100220a i q = 1 ma p_5.1.14 current consumption i q = i i ? i q i q ?815ma i q = 250 ma p_5.1.15 current consumption i q = i i ? i q i q ? 15 25 ma tle42744dv50, tle42744gv50, tle42744ev50; i q = 400 ma p_5.1.16 current consumption i q = i i ? i q i q ? 20 30 ma tle42744gv33, tle42744dv33, TLE42744GSv33; i q = 400 ma p_5.1.17 1) measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5 v. 2) not subject to production test, specified by design table 4 electrical characteristics (cont?d) v i = 13.5 v; t j = -40 c to 150 c; all voltages with respect to ground (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. dv q dt ---------- -
tle42744 electrical characteristics data sheet 11 rev. 1.2, 2014-07-03 5.2 typical performance characteristics voltage regulator current consumption i q versus output current i q current consumption i q versus low output current i q output voltage variation ? v q versus junction temperature t j dropout voltage v dr versus output current i q (5 v versions only) 01_iq_iq.vsd 0 2 4 6 8 10 12 14 16 0 100 200 300 400 i q [ma] i q [ma] v i = 13.5 v t j = 25 c 02_iq_iqlow.vsd 0 0,2 0,4 0,6 0,8 1 1,2 1,4 0 20406080100 i q [ma] i q [ma] v i = 13.5 v t j = 25 c 03_vq_tj.vsd -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 -40 0 40 80 120 t j [c] v q [%] i q = 5 ma v i = 13.5 v 150 04_vdr_iq.vsd 0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 i q [ma] v dr [mv] t j = 150 c t j = 25 c t j = -40 c
data sheet 12 rev. 1.2, 2014-07-03 tle42744 electrical characteristics dropout voltage v dr versus junction temperature (5 v versions only) maximum output current i q versus input voltage v i region of stability: output capacitor?s esr esr(c q ) versus output current i q 05_vdr_tj.vsd 0 50 100 150 200 250 300 350 400 450 500 -40 0 40 80 120 160 t j [c] v dr [mv] i q = 400 ma i q = 100 ma i q = 10 ma 0 6 _ iq max_ vi.vsd 0 100 200 300 400 500 600 700 800 900 010203040 v i [v] i q,max [ma] v q = v q,nom - 100 mv t j = -40 c t j = 25 c t j = 150 c 07_esr_iq.vsd 0,01 0,1 1 10 0 100 200 300 400 i q [ma] esr(c q ) [ ] c q = 22 f v i = 13.5 v stable region unstable region
tle42744 application information data sheet 13 rev. 1.2, 2014-07-03 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 6.1 application diagram figure 4 application diagram 6.2 selection of external components 6.2.1 input pin the typical input circuitry for a linear voltage regulator is shown in the application diagram above. a ceramic capacitor at the input, in the range of 100 nf to 470 nf, is recommended to filter out the high frequency disturbances imposed by the line e.g. iso pulses 3a/b. this capacitor must be placed very close to the input pin of the linear voltage regulator on the pcb. an aluminum electrolytic capacitor in the range of 10 f to 470 f is recommended as an input buffer to smooth out high energy pulses, such as iso pulse 2a. this capaci tor should be placed close to the input pin of the linear voltage regulator on the pcb. an overvoltage suppressor diode can be used to furthe r suppress any high voltag e beyond the maximum rating of the linear voltage regulator and protect th e device against any damage due to over-voltage. the external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances. 6.2.2 output pin an output capacitor is mandatory for th e stability of linear voltage regulators. the requirement to the output capacitor is given in ?functional range? on page 6 . the graph ?region of stability: output capacitor?s esr esr(c q ) versus output current i q ? on page 12 shows the stable operation range of the device. supply 100 nf 10f c i1 c i2 regulated output voltage i q c q <45v d i load (e.g. micro controller) gnd i i bandgap reference gnd q i current limitation temperature shutdown 22 f (esr<3 ? )
data sheet 14 rev. 1.2, 2014-07-03 tle42744 application information tle42744 is designed to be stable with extremely low esr capacitors. according to the automotive environment, ceramic capacitors with x5r or x7r dielectrics are recommended. the output capacitor should be placed as close as possible to the regulat or?s output and gnd pins and on the same side of the pcb as the regulator itself. in case of rapid transients of input voltage or load curr ent, the capacitance should be dimensioned in accordance and verified in the re al application that t he output stability requ irements are fulfilled. 6.3 thermal considerations knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: (1) with ? p d : continuous power dissipation ? v i : input voltage ? v q : output voltage ? i q : output current ? i q : quiescent current the maximum acceptable thermal resistance r thja can then be calculated: (2) with ? t j,max : maximum allowed junction temperature ? t a : ambient temperature based on the above calculation the proper pcb type and the necessary heat sink area can be determined with reference to the specification in ?thermal resistance? on page 7 . example application conditions: v i = 13.5 v v q = 5 v i q = 250 ma t a = 85 c calculation of r thja,max : p d =( v i ? v q ) ? i q + v i ? i q = (13.5 v ? 5 v) ? 250 ma + 13.5 v ? 15 ma = 2.125 w + 0.2025 w = 2.3275 w p d v i v q ? () i q v i i q + = r thja max , t jmax , t a ? p d --------------------------- - =
tle42744 application information data sheet 15 rev. 1.2, 2014-07-03 r thja,max =( t j,max ? t a ) / p d = (150 c ? 85 c) / 2.3275 w =27.93k/w as a result, the pcb design must ensure a thermal resistance r thja lower than 27.93 k/w. by considering tle42744gv50 (pg-to263-3 package) and according to ?thermal resistance? on page 7 , only the fr4 2s2p board is applicable. 6.4 reverse polarity protection tle42744 is self protected against reve rse polarity faults and allows negati ve supply voltage. external reverse polarity diode is not needed. however, the absolute maximum ratings of the device as specified in ?absolute maximum ratings? on page 6 must be kept. the reverse voltage causes several sma ll currents to flow into the ic henc e increasing its junction temperature. as the thermal shut down circuitry does not work in the re verse polarity condition, designers have to consider this in their thermal design.
data sheet 16 rev. 1.2, 2014-07-03 tle42744 package outlines 7 package outlines figure 5 pg-to252-3 5.4 ?.1 -0.05 6.5 +0.15 a ?.5 9.98 6.22 -0.2 1 ?.1 ?.15 0.8 0.15 max. ?.1 per s ide 0.75 2.28 4.57 +0.08 gpt09277 -0.04 0.5 2.3 -0.10 +0.05 b 0.51 min. +0.08 -0.04 0.5 0...0.15 b a 0.25 m 0.1 all met a l su rf a ce s tin pl a ted, except a re a of c u t. 3x (5) (4.24) -0.01 +0.20 0.9 b
tle42744 package outlines data sheet 17 rev. 1.2, 2014-07-03 figure 6 pg-to263-3 b a 0.25 m 0.1 typic a l ?.2 gpt09362 10 8.5 1) 7.55 1) (15) ?.2 9.25 ?.3 1 0...0.15 5.08 2.54 0.75 ?.1 1.05 ?.1 1.27 4.4 b 0.5 ?.1 ?.3 2.7 4.7 ?.5 0.05 1) 0.1 all met a l su rf a ce s : tin pl a ted, except a re a of c u t. 2.4 met a l su rf a ce min. x=7.25, y=6.9 a 0...0.3 b 8? max.
data sheet 18 rev. 1.2, 2014-07-03 tle42744 package outlines figure 7 pg-ssop-14 exposed pad 1 7 14 8 14 17 8 14x 0.25 ?.05 ?.05 2) m 0.15 d c a-b 0.65 c stand off 0.05 (1.45) 1.7 max. 0.0 8 c a b 4.9 ?.1 1) a-b h 0.1 2x 1) does not include plastic or metal protrusion of 0.15 max. per side 2) lead width can be 0.61 max. in dambar area bottom view ?.2 3 ?.2 2.65 ?.2 d h 6 14x 0.64 ?.25 3 .9 ?.1 1) 0. 3 5 x 45 0.1 hd 2x 0.2 c +0.06 0.19 8 max. index marking exposed diepad seating plane 6 x 0.65 = 3 .9
tle42744 package outlines data sheet 19 rev. 1.2, 2014-07-03 figure 8 pg-sot223-4 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). sot223-po v04 12 3 3 4 ?.1 0.04 0.5 min. 0.28 0.1 max. 6.5 ?.2 a 4.6 2.3 0.7 ?.1 0.25 m a 1.6 ?.1 7 ?.3 b 0.25 m ?.2 3.5 b 0...10? for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 20 rev. 1.2, 2014-07-03 tle42744 revision history 8 revision history revision date changes 1.2 2014-07-03 application information added. pg-to252-3 and pg-ssop-14 ep package outlines updated. 1.1 2010-01-13 updated version data sheet: version tle42744ev50 in pg-ssop-14 exposed pad and all related description added; 3.3v versions tle42744gv33 in pg-t o263-3, tle42744dv33 in pg-to252-3 and TLE42744GSv33 in pg-sot223-4 and all related description added 1.0 2009-01-14 initial version final data sheet
edition 2014-07-03 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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